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Sensors and Materials, Volume 31, Number 5(1) (2019)
Copyright(C) MYU K.K. All Rights Reserved.
pp. 1535-1544
S&M1877 Research Paper of Special Issue
https://doi.org/10.18494/SAM.2019.2273
Published: May 16, 2019

4.36 fJ/Conversion-step Ultralow-power 16-bit Successive Approximation Register Capacitance-to-digital Converter in 0.18 µm CMOS Process [PDF]

Jaesung Kim, Kwonsang Han, Hyungseup Kim, Byeoncheol Lee, Sangyoun Shin, and Hyoungho Ko

(Received April 13, 2018; Accepted March 20, 2019)

Keywords: capacitance-to-digital converter (CDC), SAR algorithm, ultralow-power consumption, energy efficiency, correlated double sampling (CDS)

In this paper, we present an ultralow-power 16-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors. To obtain ultralow power consumption, the CDC is designed using 0.7 V input voltage. Furthermore, the CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation and energy efficiency. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in the dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge domain. The R-2R DAC determines the lower 8-bit, and the remaining upper 8-bit is determined by the CDAC. To obtain ultralow power consumption, the minimum resistor of the R-2R DAC is 1.5 MΩ. The proposed CDC achieves a wide input capacitance range of 12.6 pF and a high resolution of 0.191 fF in simulation. The CDC is fabricated in the 0.18 μm 1P6M CMOS process with an active area of 0.63 mm2. The total power consumption of the CDC is 0.254 µW with a 0.7 V supply in simulation. The SAR CDC achieves a simulated 16-bit resolution within a conversion time of 1.125 ms and an energy-efficiency figure-of-merit (FoM) of 4.36 fJ/conversion step.

Corresponding author: Hyoungho Ko


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This work is licensed under a Creative Commons Attribution 4.0 International License.

Cite this article
Jaesung Kim, Kwonsang Han, Hyungseup Kim, Byeoncheol Lee, Sangyoun Shin, and Hyoungho Ko, 4.36 fJ/Conversion-step Ultralow-power 16-bit Successive Approximation Register Capacitance-to-digital Converter in 0.18 µm CMOS Process, Sens. Mater., Vol. 31, No. 5, 2019, p. 1535-1544.



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