4.36 fJ/Conversion-step Ultralow-power 16-bit Successive Approximation Register Capacitance-to-digital Converter in 0.18 μm CMOS Process

In this paper, we present an ultralow-power 16-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors. To obtain ultralow power consumption, the CDC is designed using 0.7 V input voltage. Furthermore, the CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation and energy efficiency. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f ) noise to achieve low-noise characteristics. The SAR algorithm is implemented in the dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance domain and an 8-bit R-2R digital-toanalog converter (DAC) in the charge domain. The R-2R DAC determines the lower 8-bit, and the remaining upper 8-bit is determined by the CDAC. To obtain ultralow power consumption, the minimum resistor of the R-2R DAC is 1.5 MΩ. The proposed CDC achieves a wide input capacitance range of 12.6 pF and a high resolution of 0.191 fF in simulation. The CDC is fabricated in the 0.18 μm 1P6M CMOS process with an active area of 0.63 mm2. The total power consumption of the CDC is 0.254 μW with a 0.7 V supply in simulation. The SAR CDC achieves a simulated 16-bit resolution within a conversion time of 1.125 ms and an energyefficiency figure-of-merit (FoM) of 4.36 fJ/conversion step.


Introduction
Micro-electromechanical systems (MEMS) sensors are receiving particular attention owing to their small size, high signal-to-noise ratio (SNR), and low cost. Among them, the capacitive sensor is widely used in accelerometers, liquid-level gauges, and pressure and humidity sensors owing to its low power, high accuracy, low-temperature dependence, and good compatibility with CMOS. (1)(2)(3)(4)(5)(6) Furthermore, these sensors are used in products such as initial measurement units, smartphones, wearable devices, and smart houses. (1,2) To use a capacitive sensor, a capacitance readout IC is required. Conventionally, the capacitance readout IC converts the capacitance to voltage and subsequently to a digital code using an analog-to-digital converter (ADC). However, the addition of an ADC results in complex circuits, larger sizes, and higher power consumption.
Recently, to address these disadvantages, the capacitance readout IC has preferably been in the form of a capacitance-to-digital converter (CDC). Unlike conventional capacitance readout ICs, CDC can convert the capacitance directly into a digital code, eliminating the need for additional ADCs, which can be beneficial in terms of complexity, size, and power consumption. (22) Because a CDC is used in products operated using batteries, low power and high-resolution characteristics are important. For high resolution, the delta sigma (∆Σ) CDC was proposed. (7,8) The ∆Σ CDC achieves high resolution through oversampling and noise shaping. However, power consumption is increased by oversampling and using the digital decimation filter, and the capacitance range is reduced to avoid a modulator overload. To achieve a wide capacitance range, a semidigital CDC that converts time to a digital code after first converting the capacitance to time was proposed. (9)(10)(11) The semidigital CDC expanded the capacitance range by converting the input capacitance to time. However, a fast digital counter and a high-frequency reference clock are required, thereby resulting in larger jitter noise and power consumption. To achieve good energy efficiency, a successive approximation register (SAR) CDC was proposed. (12) The schematic of the conventional SAR CDC is shown in Fig. 1. Because the sensor capacitance (C s ) is connected to the high-impedance node V x , the sampled charge is redistributed to all capacitances connected to node V x including that of the parasitic capacitor (C p ), which can be very large, especially for off-chip capacitive sensors. This offset voltage causes a conversion error that eventually leads to a reduction in resolution. To address the offset error limitation, a method using a charge amplifier before a comparator was proposed. (13) However, the architecture has reduced the energy efficiency owing to the use of the powerconsuming operational transconductance amplifier (OTA). We herein present the ultralow-power SAR CDC for capacitive sensors. The proposed CDC increases the energy efficiency by applying the SAR algorithm and creates a more energyefficient comparator by organizing the sensors in the capacitive sensing amplifier (CSA) and dynamic latch structures, thereby rendering them insensitive to offsets caused by the parasitic capacitor. In addition, the CSA implemented the ultralow power using the inverter-based amplifier. Furthermore, the CSA uses a designed correlated double sampling (CDS) technique to reduce the offset and flicker noise (1/f ). The conventional SAR algorithm uses only the capacitor digital-to-analog converter (CDAC) using the cap array, and the resolution is limited owing to the parasitic cap that was generated by the cap array. To address this limitation, the proposed SAR algorithm is implemented in the dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance domain and an 8-bit R-2R DAC in the charge domain. The CDC is optimized and implemented in 0.18 µm CMOS technology and achieves an energy-efficiency figure-of-merit (FoM) of 4.36-fJ/conversion step.

Architecture of the proposed SAR CDC
A schematic of the proposed 16-bit SAR CDC circuit and the timing diagram are shown in Fig. 2. It comprises a CSA, dynamic latch, SAR control logic, 8-bit coarse programmable capacitor array (CDAC), and 8-bit R-2R DAC.
To achieve energy efficiency, the CSA is a conventional inverter-based amplifier. The inverter-based amplifier can be implemented in the self-biased form. Furthermore, the sourcing current can be reused as the sinking current. This results in excellent noise efficiency factor (NEF) characteristics and good energy efficiency.

Operation of the proposed SAR CDC
The circuit operation is performed in two phases. The SAR CDC requires non-overlapping clocks, P 1 and P 2 , as well as a SAR clock. The operation of the input stage of the proposed SAR CDC is shown in Fig. 3. P 1 is the sampling phase in which the sensor capacitor and the DAC are charged. Subsequently, the CSA operates as a unit gain buffer. The stored charge is given by Furthermore, owing to the CDS technique, the feedback capacitor (C f ) is charged with lowfrequency noise. P 2 is the amplifying phase in which the charge on the sensor capacitor and DAC is redistributed to the C f . The charge is given by Furthermore, the low-frequency noise stored in the C f is subtracted. Because charge is conserved, from Eqs. (1) and (2), the output voltage (V OUT ) of the CSA is Thus, the differential voltage at the comparator input terminals (∆V) is given by The comparator input terminals (∆V) are subsequently converted to a digital code through the comparator. The comparator used in the proposed CDC is shown in Fig. 4. The comparator Fig. 3. Operation of the input stage. Fig. 4. Schematic of the dynamic latch comparator. uses a dynamic latch structure to obtain good energy efficiency. The comparator output enters the SAR algorithm of the 16-bit SAR logic, with the top 8-bit controlling the CDAC and the bottom 8-bit controlling the R-2R DAC. The CDAC operates in the capacitance domain with the upper 8-bit, and the R-2R DAC operates in the charge domain with the lower 8-bit. In the charge-domain operation, charge is stored to C DAC in proportion to the output voltage of the R-2R DAC in the P 1 phase. Furthermore, the stored charge is redistributed to the CSA input in the P 2 phase. In the proposed CDC, the C DAC is 49 fF, the input capacitance range is 12.6 pF, and the high resolution is 0.191 fF.

Design of the proposed SAR CDC
The layout of the proposed ultralow-power SAR CDC is shown in Fig. 5. The entire layout consisted of the CSA, comparator, timing generator, CAP DAC, R-2R DAC, and SAR logic. The proposed SAR CDC is designed for the 0.18 µm 1P6M CMOS process with an active area of 0.63 mm 2 .

Simulation results of the proposed SAR CDC
The simulation results of the proposed SAR CDC are shown in Fig. 6. Figures 6(a) and 6(c) show the change in input capacitance over time. The change in input capacitance was from 0 to 12.6 pF in the sine and ramp waveforms. Figures 6(b) and 6(d) show the digital output code of the proposed SAR CDC.
The energy efficiency of the proposed SAR CDC is evaluated using the energy-efficiency FoM. The FoM is given by where P avg is the average power, T conv is the conversion time, and R is the effective resolution in bit. Furthermore, the effective resolution is given by 1.76 6.02 where the SNR is given by The absolute resolution was obtained as the rms value of the output code after setting the input capacitance. When the transient noise was 10 mHz f min, 100 kHz f max, and 1 f seed, the digital output code is as shown in Fig. 7. The simulation results showed that the output noise was less than 1 least significant bit (LSB). Thus, the effective resolution was expressed in 16 bits. The proposed SAR CDC has a power of 0.254 µW, a conversion time of 1.125 ms, and an effective resolution of 16 bits, resulting in a 4.36-fJ/conversion step in simulation. A performance summary of the simulated parameters and comparisons with state-of-the-art CDCs are shown in Table 1. In addition, Fig. 8 shows a comparison of the FoM and capacitance range,    which represents the energy efficiency. In Table 1, the power consumption of the proposed SAR CDC is 0.254 µW, which is much lower than that of the SAR structures. As shown in Fig. 8, the proposed SAR CDC achieves a FoM of 4.36 fJ/conversion step, which is much lower than those in previous works, resulting in excellent energy efficiency in the reasonable capacitance range.

Conclusion
We herein presented the ultralow-power 16-bit SAR CDC for the capacitive sensor. The proposed SAR CDC used the inverter-based CSA, dynamic latch comparator, and SAR algorithm for energy efficiency. The CSA also used CDS techniques to reduce the offset and the flicker noise (1/f ). Additionally, the SAR algorithm was implemented in the dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance domain, and an 8-bit R-2R DAC in the charge domain to reduce the offset caused by the parasitic cap on the CDAC. The proposed CDC was designed for the 0.18 µm 1P6M CMOS process with an active area of 0.63 mm 2 . The total power consumption of the proposed CDC was 0.254 µW with a 0.7 V supply in simulation. Furthermore, the proposed CDC achieved an energy-efficiency FoM of 4.36-fJ/conversion step in simulation.