ISSN 0914-4935

Sensors and Materials
is an international peer-reviewed open access journal to provide a forum for researchers working in multidisciplinary fields of sensing technology.
Sensors and Materials
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Sensors and Materials,
Volume 30, Number 8(1) (2018)

Copyright(C) MYU K.K. All Rights Reserved.
pp. 1765-1773
S&M1633
https://doi.org/10.18494/SAM.2018.1868
Published: August 15, 2018

31.6 pJ/Conversion-step Energy-efficient 16-bit Successive Approximation Register Capacitance-to-digital Converter in a 0.18 μm CMOS Process [PDF]

Youngwoon Ko, Hyungseup Kim, Yeongjin Mun, Byeoncheol Lee, Gyungtae Kim, Woo Suk Sul, Boung Ju Lee, and Hyoungho Ko

(Received April 5, 2017; Accepted February 16, 2018)

Keywords: capacitance-to-digital converter (CDC), energy-efficient CDC, successive approximation register (SAR), low power, correlated double sampling (CDS)

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a 0.18 μm 1P6M complementary metal–oxide–semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is 86.4 μW with a 1.8 V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.125 ms and an energy-efficiency FoM of 31.6 pJ/conversion-step.

Corresponding author: Hyoungho Ko


Cite this article
Youngwoon Ko, Hyungseup Kim, Yeongjin Mun, Byeoncheol Lee, Gyungtae Kim, Woo Suk Sul, Boung Ju Lee, and Hyoungho Ko, 31.6 pJ/Conversion-step Energy-efficient 16-bit Successive Approximation Register Capacitance-to-digital Converter in a 0.18 μm CMOS Process, Sens. Mater., Vol. 30, No. 8, 2018, p. 1765-1773.


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