Bridgeless Single-stage Step-down Power Factor Corrector under Synchronous Switching Control Scheme

In this paper, a novel bridgeless power factor corrector (PFC) is proposed. The PFC can shape the waveform of the input current to be sinusoidal and in phase with the AC input voltage simply by sensing of the AC voltage, input current, and output voltage. That is, it is able to achieve a unity power factor. As compared with conventional PFCs, the proposed PFC possesses the particular features of high step-down voltage ratio, being bridgeless, galvanic isolation, and leakage energy recycling. All the active switches in the proposed PFC can be operated under an identical control signal. In addition, the output voltage can be regulated only by single-loop control, instead of dualor multiloop control. Therefore, the control scheme for the PFC is simple and much easier to carry out. The operation principle, theoretical analysis, and hardware validation to verify the proposed PFC are described.


Introduction
Power-electronics-based devices have been applied in various fields from household appliances to industry equipment, and the total number of relevant products is increasing dramatically. Among them, converters to convert AC power to DC are widely required, especially for a low DC output voltage, such as for battery chargers, LED drivers, and computer power supplies.
AC-to-DC converters conventionally include a bridge rectifier and a huge filter capacitor. Similarly to the power-stage structure shown in Ref. 1, this configuration is simple, cheap, and without the need of an extra control circuit. Nonetheless, it may lead to serious harmonic distortion and results in a low power factor. Adding a current-shaping circuit at the input can not only improve the power factor but also reduce harmonic distortion. Nevertheless, power factor correctors (PFCs) are generally still based on a bridge configuration. (2)(3)(4)(5)(6)(7) The efficiency is therefore rather low. Furthermore, if a PFC is a boost type, the output DC voltage will be higher than the input, even with the obvious advantage of a continuous input current. To deal with a low-voltage load, buck-type PFCs are options, (8)(9)(10)(11)(12)(13) but the input current will be discontinuous and an active switch has to be driven on the high-voltage side. Therefore, a cascaded filter on the AC input side is necessary for achieving a better power factor.
To obtain a continuous input current and lower the output voltage simultaneously, a twostage PFC has been considered. (14)(15)(16)(17)(18)(19)(20) However, the requirement of more components and the associated lower efficiency are both its main drawbacks. This paper proposed a bridgeless single-stage step-down PFC (BSSPFC) with the feature of galvanic isolation to overcome the aforementioned problems. A high-frequency transformer is incorporated to feature galvanic isolation, the core material of which is Mn-Zn ferrite. All the active switches in the BSSPFC can be controlled simply by synchronous driving, which simplifies the control mechanism. In addition, the BSSPFC is capable of stepping down the input voltage significantly and improving the converter efficiency effectively. The volume of the AC input filter can also be reduced while operating in continuous conduction mode (CCM).

Main Structure and Steady-state Analysis
The structure of the proposed BSSPFC is shown in Fig. 1, which is derived from the integration of a single-ended primary-inductor converter (SEPIC) and a flyback converter. The frond-end of the BSSPFC can be regarded as a modified bridgeless SEPIC in charge of performing power factor correction, and the downstream is a flyback-based configuration for achieving a higher step-down voltage ratio and galvanic isolation. The output power of the BSSPFC can be raised when the current of the input inductor L in is in CCM. In CCM, the current stress of active switches can be alleviated and the size of the EMC/EMI filter is also reduced. In this section, the operation principle and voltage gain will be discussed, where the following assumptions are made. 1) All capacitors are large enough to guarantee that the voltages across C 1 , C 2 , and C o can be regarded as constant. 2) Semiconductor devices such as diodes and switches are ideal.
3) The turn ratio n is equal to N 2 /N 1 . 4) The duty ratio of the converter is D. 5) The switching period is defined as T.

Operation principle
The operation of the BSSPFC can mainly be divided into three modes over one switching cycle. Figure 2 depicts the conceptual key waveforms, which are the control signal and current of switch SW 1 , the current of diode D 4 , and the current of inductor L 2 . This figure has been included to aid understanding of the converter operation. The converter operation is discussed mode by mode in the following.
Mode 1 [t 0 -t 1 ] ( Fig. 3): At the beginning of Mode 1, switches SW 1 and SW 2 are turned on simultaneously and diodes D 3 and D 5 are in the ON-state. Inductor L in is magnetized by v ac and inductor L 1 is charged by capacitor C 2 . Capacitor C 1 transmits its stored energy to inductor L 2 through the transformer. Meanwhile, L m and L k absorb energy from capacitor C 1 .
Mode 2 [t 1 -t 2 ] (Fig. 4): In mode 2, switches SW 1 and SW 2 are both in the OFF-state and therefore diodes D 3 , D 4 , and D 6 are forward biased. Inductor L in releases energy to capacitors C 1 and C 2 . At the same time, capacitor C 2 also draws energy from L m and L k . Mode 2 ends when the two currents flowing through inductors L m and L k drop to zero.
Mode 3 [t 2 -t 3 ] (Fig. 5): After L m and L k fully discharge their stored energy, the operation mode of the BSSPFC enters Mode 3. During this mode, the circuit condition is the same as that in Mode 2 except for inductors L m and L k . Mode 3 continues until the active switches are turned on again and then the converter operation over one switching cycle is completed.

Voltage gain derivation
The following is the voltage gain derivation of the proposed BSSPFC. Voltage polarity and current direction definitions are shown in Fig. 1. Applying the volt-second balance criterion to inductors L in , L 1 , and L 2 and finding the voltage across the capacitor C 1 are the key points of this theoretical derivation.
1) Volt-second balance on L in When SW 1 is closed (0 ≤ t ≤ DT), the voltage across input inductor L in is equal to the input source, that is, (1) According to Eq. (1), the variation of the inductor current (∆i Lin ) on during the ON-state interval is When SW 1 is OFF (DT ≤ t ≤ T), input inductor L in will charge capacitors C 1 and C 2 . Therefore,   2 From Eq. (3), the variation of the inductor current (∆i Lin ) off over the OFF-time interval can be estimated as Under a steady-state condition, the current increment and decrease on inductor L in , (∆i Lin ) on and (∆i Lin ) off , respectively, will be identical. Therefore, Solving Eq. (5) yields 2) Volt-second balance on L 1 When SW 1 is conducted (0 ≤ t ≤ DT), capacitor C 2 will be in parallel with inductor L 1 . That is, According to Eq. (7), the current increment on the inductor, (∆i L1 ) on , during this time period is ( ) When switch SW 1 is open during the time period DT ≤ t ≤ (1 − D)T, inductor L 1 provides energy to C 1 and thus, 1 1 From Eq. (9), the inductor current drop, (∆i L1 ) off , during this time period can be calculated as Based on the volt-second balance, the net change of the inductor current has to be zero. Accordingly, ( ) ( ) 1 1 2 After solving Eq. (11), the relationship between v C1 and v C2 can be expressed as 3) Volt-second balance on L 2 When SW 1 is ON, the voltage across inductor L 2 will be According to Eq. (13), the variation of the inductor current (∆i L2 ) on during this ON-state period can be expressed as When the switch is open, inductor L 2 will provide energy to C o and the voltage of Thus, the current drop on the inductor current, (∆i L2 ) off , is computed as In steady-state operation, the magnitudes of (∆i L2 ) on and (∆i L2 ) off will be identical and the following relationship holds: Solving Eq. (17), one can obtain

4) Capacitor voltage and converter gain
Substituting Eq. (18) into Eq. (6) gives the voltage across capacitor C 1 : Likewise, the voltage across capacitor C 2 can be obtained by substituting Eq. (12) into Eq. (18). Accordingly, Capacitor C 2 is irrelevant to the voltage gain and only performs energy recycling for leakage inductance and magnetizing inductance. According to Eqs. (18) and (19), the voltage gain of the BSSPFC is determined as In addition, there are two active switches in the proposed circuit. The voltage stresses of the two switches are identical and are the series voltages across capacitors C 1 and C 2 . That is,

Experimental Results and Discussion
To verify the feasibility of the proposed structure, a 200 W prototype dealing with a universal-line input is built, tested, and measured. Figure 6 shows the waveforms of input voltage v ac and current i Lin , when the AC mains is 90 V rms . As shown in Fig. 6(a), the input current is purely sinusoidal and in phase with the AC mains voltage. Figure 6(b) shows the measured output voltage and current, which indicate that a near ripple-free feature can be achieved at the DC output. Figures 7(a) and 7(b) show the voltages and currents of the input and output, respectively, when the AC mains voltage increases to 110 V rms . From Fig. 7, a high input power factor and near ripple-free feature are still accomplished. Figures 8 and 9 show the practical measurements performed at inputs of 220 and 264 V rms , respectively, both of which reveal that high performance can also be achieved by the proposed BSSPFC. Figure 10 is the transient response when the output power is stepped up from half load to full load. For the case of 220 V rms input and 200 W power rating, the measured result for SW 1 is shown in Fig. 11.     From the measured waveform, it is found that the active switch is free from spikes. Figure 12 depicts the measured efficiency of the prototype under different input voltages, which reveals that the peak efficiency is up to 91.8% at 264 V rms line voltage. Figure 12 also reveals that when the input voltage is higher, the current in the entire power stage is lower. Accordingly, conduction loss therefore drops and efficiency is raised. In addition, a photo of the prototype BSSPFC is shown in Fig. 13.

Conclusions
A high step-down bridgeless PFC is proposed, which possesses the following advantages: fewer rectifying diodes, a single power stage, galvanic isolation, active switches in synchronous control, universal-line input from 90 to 264 V rms , and a simple control mechanism. The BSSPFC can accommodate universal-line input, and moreover, even at a high input voltage, a high power factor and near ripple-free output can still be obtained. Since fewer components are used, the cost can accordingly be lowered and conversion efficiency is improved. To verify the feasibility of the BSSPFC, hardware measurements from a 200 W prototype are carried out. The experimental results demonstrate the characteristics of the BSSPFC, and the average efficiency achieved is up to 90.08%.