Design of Planar Si Thermoelectric Generators with Phononic Crystal Patterning

This paper presents the design and optimization of planar poly-Si thermoelectric generators (TEGs) for energy harvesting application. Temperature and electric potential distributions are simulated using material parameters, which were experimentally obtained from test structures, by the finite element method to evaluate the performance of TEGs. TEGs with unpatterned membranes or membranes with phononic crystal (PnC) nanostructures are investigated to evaluate the increase in power density by nanopatterning. The power density is increased by PnC nanopatterning with larger holes and the optimal bridge length decreases owing to a higher thermal resistance. The series of simulations shows that nanopatterning increases the power density 2.5 times at a smaller bridge length and is also advantageous from the viewpoint of mechanical strength.


Introduction
The concept of smart dust, which was followed by the internet of things (IoT) and ubiquitous computing, has been waiting for advanced technologies including energy harvesting for practical use in society for more than two decades. Thermoelectrics is one of the promising energy conversion technologies to realize an energy autonomous wireless sensor node for this purpose. Various thermoelectric materials were developed and their thermoelectric properties were investigated. (1)(2)(3) Silicon (Si) is the most practical material in electronics, but not for thermoelectric application at room temperature owing to its very high thermal conductivity. (4,5) However, researchers found that thermal conduction in nanostructures is much lower than in bulk and can be dramatically reduced by nanostructuring. (6)(7)(8)(9)(10) This is due to the enhancement of diffusive surface scattering, and the figure of merit ZT can be as high as 0.6 at room temperature in nanowires. (11,12) We investigate thermal phonon transport and heat conduction in nanostructured Si membranes, especially in membranes with PnC nanostructures, and develop planar Si thermoelectric devices. (13)(14)(15)(16)(17) A planar Si thermoelectric device can be fabricated using CMOS and micro-electromechanical system (MEMS) technologies, and is suitable for low-cost mass production. (18,19) In addition, the high reliability and environmental friendliness of Si are also advantageous for its widespread use in the environment and society. However, a planar device requires careful thermal design to generate sufficient electric power to drive microelectronic devices, because the temperature difference between the edges of a bridge structure of a thermoelectric membrane is normally small. Xie et al. designed and fabricated devices with peripheral cavity structures formed by CMOS and MEMS processes, and reported their high performance. (20,21) We also fabricate planar devices but with nanostructuring in Si membranes to increase the thermal resistance, which results in higher power generation.
In this work, we report the design and simulated performance of planar Si thermoelectric devices with PnC nanostructures at room temperature based on parameters experimentally obtained using test structures. A thermal analysis was performed by the finite element method for various bridge lengths for optimization. We also investigated the importance of a substrate and compared the maximum power density at the optimum bridge length.

Simulation and System
In this section, the simulated structures and details of the simulation are explained. A threedimensional model [50 × 30 × (30-72)] µm 3 was built as shown in Fig. 1(a). The simulated system is composed of device [ Fig. 1(b)], air, and substrate parts. The boundary condition in the in-plane directions is periodic, but the upper plane of the air part and the bottom plane of the substrate part were fixed and their temperature difference (ΔT env ) was set at 10 K. In this simulation, the substrate was heated and heat escaped to the air via gas-solid heat exchange with natural convection. The thermal analysis in the solid was based on the diffusive model using Eq. (1) with the density ρ and heat capacity C p , The details and dimensions of the device part are shown in Fig. 1(b). Two pairs of n-and p-type poly-Si thermoelectric generators are fabricated on a SiO 2 sacrificial layer and connected by Al electrodes. PnC nanostructures are formed in the bridges and function as thermoelectric materials. Etching slits are formed in the central island part to isolate it from the substrate. The width of the bridge is 12 µm and the widths of the Al electrodes in the central island and on SiO 2 are 4 and 6 µm, respectively. The thicknesses of the poly-Si, Al electrode, SiO 2 , air box, and substrate are 300 nm, 200 nm, 2.5 µm, 25 µm, and 25 µm, respectively. The material and other parameters are summarized in Table 1. Thermal analysis was performed by the finite element method for unpatterned membranes and membranes with PnCs with circular airholes with radii of 60, 100, and 120 nm. Each PnC has arrays of through holes aligned as a square lattice with a periodicity a of 300 nm in the suspended membrane. The electrical conductivity σ, thermal conductivity κ, and Seebeck coefficient S were taken from our previous work, (14) and R cont was taken from the literature. (20)

Simulation Results and Discussion
Temperature and electric potential distributions in the device part were simulated at an environmental temperature difference ΔT env of 10 K (Fig. 2). The temperature distribution simulated for a structure with a PnC structure with airholes of r = 120 nm is shown in Fig.  2(a). The poly-Si part on the SiO 2 layer is hotter and the suspended central island is cooler, but the temperature difference between edges of the suspended thermoelectric material, ΔT mat , is only 560 mK, which is only about 6% of ΔT env . However, ΔT mat is increased 3.2 times by PnC nanopatterning compared with the increase for an unpatterned membrane at the bridge length L = 7 µm.   This finding indicates that the thermal design is very important for a planar device and emphasizes the importance of the high thermal resistance of the bridges. The simulation also gives the electrical potential distribution shown in Fig. 2(b). One pair of n-and p-type thermocouples generates 180 µV. The p-type Si bridge generates a higher thermoelectric voltage than the n-type Si bridge owing to its larger Seebeck coefficient. The open-circuit output voltage V 0 is given by V 0 = (|S n | + S p ) ΔT mat , where S n and S p are the Seebeck coefficients for the n-and p-type poly-Si membranes, respectively.
The output power P 0 was estimated for unpatterned and PnC-nanopatterned membranes using various bridge lengths to optimize at a fixed bridge width of 12 µm. P 0 was calculated with load resistance given by the internal electrical resistance of one unit, R total , and P 0 is given by (2) Figure 3 shows the length dependence of the power density. When the bridge is short, ΔT mat is low owing to a low thermal resistance. As the bridge becomes longer, ΔT mat saturates and the foot print of one unit becomes unnecessarily large. Therefore, an optimum bridge length exists and continuously decreases as the thermal resistivity of the bridge increases, i.e., for a PnC nanostructure with larger holes. The maximum power density is increased 2.5 times by PnC patterning. This increase mainly stems from a larger ΔT mat and an increased ZT, both of which result from thermal conductivity reduction by nanopatterning. In addition, a shorter bridge is better for practical use in a harsh environment because the bridge is mechanically more robust. Therefore, nanopatterning is an effective approach for improving the performance of a planar thermoelectric device as long as the process cost is low. The nanoholes used in this study are large enough to be fabricated by nanoimprint lithography, which enables low-cost large-area patterning. Finally, we investigated the importance of the substrate in the thermal design. As the thermal conductivities (κ substrate ) of the substrate, 1.38, 2, 27, and 130 W/mK were used as the values of SiO 2 , amorphous Si (a-Si), Al 2 O 3 , and single-crystalline Si, respectively. Figure 4 shows that a higher power density is achieved with a thermally more conductive substrate. This is because a higher thermal gradient is formed in the thermoelectric material. It is also found that the power density does not change markedly above κ substrate ~ 10 W/mK. This conclusion is also valid for a 500-µm-thick standard substrate. This is a useful finding because the substrate may not necessarily be thermally highly conductive, and thus low-cost ceramics can also be used as substrates.

Conclusions
Planar poly-Si thermoelectric devices were designed and their performance at room temperature was investigated by thermal analysis using the finite element method. The thermal design to increase the temperature difference between the edges of a suspended thermoelectric material is very important for the enhancement of power generation. PnC patterning with a periodicity of 300 nm reduces the thermal conductivity and results in a ZT improvement and a 2.5-fold power generation enhancement. The analysis also indicates that the substrate does not necessarily have to be thermally conductive; a low-cost substrate with a moderate thermal conductivity is available. The nanopatterning of a thermoelectric material by a low-cost and large-area fabrication process is a practical approach for obtaining high-performance planar thermoelectric devices.  Patrick Ruther studied physics and received the Ph.D. degree in mechanical engineering in 1996. Between 1996 and 1998, he was PostDoc at the Research Center Karlsruhe, Germany, developing LIGA-based microoptical components. Since October 1998, he is a senior scientist in the Department of Microsystems Engineering (IMTEK), University of Freiburg. His focus is on the design, fabrication, and characterization of CMOS-compatible MEMS devices including microoptical functionality for biomedical applications, e.g., neuroscience and optogenetics. He coordinated the EU project NeuroSeeker targeting the next generation of neural probes comprising electronic and optical functionalities, and is a member of the BrainLinks-BrainTools Cluster of Excellence at the University of Freiburg. He is a cofounder of the spin-off company ATLAS Neuroengineering, Belgium.
Oliver Paul received his Diploma (Physics) and Ph.D. degrees from ETH Zürich, Switzerland, in 1986 and 1990, respectively. From 1990 to 1998, he has held postdoctoral, group leader and lecturer positions at the Fraunhofer Institute for Solar Energy Research in Freiburg Germany, and at ETH Zürich. Since 1998, he has been a professor, the director of the Department of Microsystems Engineering and the dean of the Faculty of Engineering at the University of Freiburg. He is an initiator and member of the Cluster of Excellence BrainLinks-BrainTools and has co-founded the companies Sensirion AG and Atlas Neuroengineering. His research interests are in microfabrication technology, MEMS for neuroscience, and semiconductor microsensors from their foundations to calibration. (paul@imtek.uni-freiburg.de)