Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET

1Department of Electronic Engineering, National Kaohsiung Normal University, No. 62, Shenjhong Rd., Yanchao District, Kaohsiung 824, Taiwan 2Department of Electrical Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nanzih District, Kaohsiung 811, Taiwan 3National Nano Device Laboratories (NDL), National Applied Research Laboratories, No. 26, Prosperity Road I, Hsinchu Science Park, Hsinchu 300, Taiwan


Introduction
FinFETs are considered a promising candidate for device scaling that surpasses the framework of traditional planar transistors and has a better gate controlling capability, repressing short-channel effects (SCEs) and hot carrier effects (HCEs), and improving the subthreshold swing (SS). (1)(2)(3)(4)(5) Even though fin-based structures may be superior electrically, they are less robust than planar structures mechanically, which may give rise to some unexpected failure mechanisms. (6) Prior studies indicate that mechanical stress shows a great impact on the electrical behavior. In traditional planar MOSFETs, thermal annealing is considered to expand the filler in shallow trenches and squeeze it; thus, the channel region is subjected to a compressive stress. (7) A typical fin bending may lead to electrical or physical failure. Its leaning angle forms an asymmetric depletion area and makes the leakage current larger than expected. (8) On the other hand, tensile and compressive stresses, which are two components of mechanical stress, will respectively improve electron and hole mobilities. (9,10) Stresses are intentionally introduced into the device channel by means of a silicon-carbon (SiC) source and drain (S/D), a strained cap layer, shallow trench insulation (STI), and so forth during the transistor fabrication process. In addition, lattice-mismatched SiC regions also induce stress in the Si channel along the width (transverse) and vertical directions. (11) In fact, with the continuous shrinking of the feature size, the STI stress effect becomes significant. (12) However, this behavior is much different from those of FinFETs and MOSFETs. In this work, the electrical and reliability analyses of tri-gate FinFETs affected by different active surface areas (SAs) were studied. Figure 1 shows a TEM image of the tri-gate FinFET used in this study. The channel length, fin width, and fin height of the device were 16, 10, and 42 nm, respectively. The surface orientation of the fin sidewall is (110), while the channel direction is <110>. After FinFET device fabrication, SiN was covered as a contact etch stop layer (CESL). The CESL obtained by thermal CVD has tensile stress due to the manufacturing process. SA was defined as the distance from the gate to the edge of shallow trench isolation (STI), as shown in Fig. 2, and different SAs of 0.098, 0.386, and 3.842 µm were utilized.

Experimental Methods
In this work, the electrical properties of FinFET devices were measured using a semiconductor parameter analyzer (Agilent-B1500A) at room temperature. During hot carrier injection (HCI) stress measurement, the drain and gate voltages were set as V D = V G = 1.6 V with the grounded source and body. I-V curves were measured at certain stress time intervals. . It was observed that V TH increases with SA, while SS is similar to the variation in SA. However, a reduction in drain current was observed with increasing SA. All samples are fabricated under the same conditions except for SA. As a result, the increase in V TH and the reduction in I D might be due to the influence of SA. On the other hand, similar SS values also indicate that different SAs did not affect the interface quality of devices.  HCI was then utilized to investigate the reliability of FinFET devices with different SAs. The I D -V G curves obtained before and after 6000s HCI are plotted in Fig. 5. The positive V TH shift during HCI stress indicates that the injected electrons were trapped in the gate dielectric layer. On the other hand, SS degradation reveals that impact ionization, which induces the generation of the interface state, occurs in FinFET devices during HCI stress. (2) It was observed that the FinFET device with a smaller SA shows a more severe degradation of V TH and the subthreshold slope. The V TH shift and SS variation versus stress time were extracted and are shown in Figs. 6(a) and 6(b), respectively. A V TH shift of 441 mV was found in the device with SA = 0.098 µm, while a V TH shift of 327 mV was observed in the device with SA = 3.842 µm. On the other hand, the increase in SS variation was determined to be 69 mV for the device with SA = 0.098 µm and 42 mV for the device with SA = 3.842 µm. It was observed that the FinFET device with a larger SA shows a higher reliability.   To examine the effect of different SA specifications, the schematic diagram of SA-induced channel stress components is shown in Fig. 7. The FinFET device used in this work was covered with SiN deposited in a furnace, thus resulting in tensile stress above the gate, which is expressed as T in Fig. 7. The tensile stress above the gate and S/D is expected to introduce a compressive stress to the channel, which is expressed as C in the diagram. As a result, a compressive stress to the channel is expected as the influence of SA. With increasing SA, the larger area covered by the CESL is expected to cause a higher tensile stress above the gate. The larger bending above the gate would lead to a higher compressive stress to the channel.

Results and Discussion
The reliability improvement of FinFET devices with the increase in SA can be explained as follows. With the increase in SA, the higher compressive stress reduces the electron mobility in the channel of nFinFETs. The reduced electron channel mobility results in a weaker   ionization impact during HCI stress, which inhibits the generation of the interface state and thus suppresses subthreshold slope degradation. On the other hand, fewer electrons are injected and trapped into the gate dielectric layer owing to the slower channel electrons, decreasing the positive shift of V TH under HCI stress.
To verify the effect of compressive stress under different SA specifications, FinFET devices with different channel lengths were studied in this work, and the I D -V D curves obtained at L = 16 and 20 nm are respectively shown in Figs. 8(a) and 8(b). A reduced drain current was observed in the device with SA = 3.842 µm as compared with that obtained with SA = 0.098 µm, and the degradation rates were determined to be 5.0 and 7.8% for FinFET devices with L = 16 and 20 nm, respectively. These results could be explained by SA-induced compressive stress. For the longer channel device, the tensile stress provided by the CESL is enhanced by the larger area above the channel. The larger tensile stress above the gate introduces a higher compressive stress in the channel. A more severe drain current degradation is expected in the longer channel  device owing to the higher compressive stress, and the higher compressive stress reduces the electron mobility more effectively. As a result, a more severe I D degradation for the longer channel with increasing SA could be explained.

Conclusions
N-type FinFET devices with different SAs were studied in this work. Compressive stress was found in the channel after CESL deposition. A large SA is considered to introduce a high compressive stress to the channel, thus reducing the channel electron mobility. As a result, a reduced device performance but an improved reliability is expected for FinFET devices with larger SAs.
Corporation (TSMC) Research and Development Division as an intern to research sub-um CMOSFETs. He also joined the United Microelectronic Corporation Technology & Process Development Division as a research staff member to research and develop logic, embedded DRAM, SOI, and 90 nm transistor technological applications. He is currently a full professor of the Electrical Engineering Department and the Dean of Engineering in National University of Kaohsiung. He is also the Chair of the IEEE EDS Tainan Chapter. He has published 2 edited books, over 100 peer-reviewed papers, 3 book chapters, and over 80 patent applications. His recent work is in the field of nanoscaled CMOSFETs, SOI MOSFETs, and FinFETs.