Study of an X-ray/Gamma Ray Photon Counting Circuit Based on Charge Injection

A direct charge-to-digital converter (QDC) based on charge injection for an X-ray/gamma ray photon counting detector is introduced in this paper. The proposed circuit is a direct conversion circuit unlike conventional indirect circuits. Direct charge signal processing does not lose time because it accomplishes conversion and resets simultaneously and starts the conversion without waiting for all the photon energy to be converted into charge. This conversion behavior was verified by simulating a direct QDC circuit. Moreover, in the simulation, the effect of the dark current in the detector was taken into consideration and an appropriate compensation method for this was proposed. An experimental circuit was built and tested with discrete components to confirm coincidence with the simulated results. Direct conversion is simpler than indirect conversion, and the resultant circuit contains fewer electronic components than an indirect converter. This circuit is suitable for high-density imaging sensor design. In addition, this architecture ideally counts generated charges individually, which is valuable for the analysis of charge drift inside the detector.


Introduction
Various types of detectors exist for X-ray/gamma ray and they are categorized as either direct or indirect conversion. Direct detectors directly convert X-ray/gamma ray photons into electron-hole pairs that drift towards the electrode as a result of a reverse bias applied to the detector. An advantage of direct detectors is that they can achieve higher efficiency in the detection of absorbed photons and higher spatial resolution than indirect detectors because this eliminates intermediate conversions. (1,2) However, conventional read-out circuits for direct detectors do not perform direct conversion in pulse processing. The read-out circuit is required to detect charge and quantitatively measure it. The output charge from one photon is inadequate to be considered as current without amplification; therefore, charge-sensitive amplifiers (CSAs) are used in many photon counting applications. (1,3,4) A CSA collects and converts charge to voltage, and the voltage is converted to a digitized code by an analog-to-digital converter (ADC). Furthermore, resetting the circuit is essential for CSA to avoid saturation because it stores the charge and the charge is unipolar. To continue the stepwise process, the charge must be returned rapidly to zero; this reset causes dead time and limits conversion over that period of time. (3) The conventional sensing system of direct X-ray/gamma ray detectors is not strictly a direct converter because of voltage pulse processing. Charge and voltage pulse processings have their own advantages and disadvantages, but direct conversion can further minimize losses due to intermediate conversion. The main inevitable disadvantages of voltage pulse processing are wider pulse, ballistic deficit due to fast shaping, (5) and dead time caused by reset; all these factors add up to significant losses in time. Conversely, charge pulse processing does not suffer loss of time because conversion and reset can be achieved simultaneously. Consequently, an additional reset circuit is not required, and the transient response of the pulse disappears (described in Sect. 2). Therefore, a charge read-out circuit that performs charge pulse processing appears promising for X-ray/gamma ray photon counting circuits for direct conversion.

Ideal Charge Read-out Circuit
An easy way to build a charge read-out circuit is to eliminate the voltage-to-current converter from the voltage ADC. However, if a sample-and-hold circuit precedes the ADC, the circuit causes dead time and timing complications during sampling because of the random nature of the input signal. The circuit shown in Fig. 1(a) can be used for charge read-out without sample-and-hold. The main components of this circuit are a detector with capacitance C det and a charge injection circuit (CIC). The charge generated in the detector is stored in C det and then the CIC counts the amount of charge as the rate e/T s [C/s], where e is the elementary charge and T s is unit time. Counting and reset are carried out at the same time; however, the circuit cannot realize when it should start and stop counting. Consequently, an additional comparator and switch are required in the circuit. The comparator should detect e as a unit charge and turn its output to high, so the threshold voltage V th should then be equal to e/C det [V]. The switch is closed and CIC functions while C det has at least the unit charge e. The output of this circuit is the time-modulated output of the comparator similar to pulse width modulation. The time of a comparator's high output corresponds to the amount of generated charge. Therefore, no additional multibit voltage ADC is required. Figure 1(b) shows an example of the time diagram for a single conversion. The top graph of Fig. 1(b) shows the input of charge by a single photon, the middle graph shows the voltage of the read-out node, and the bottom graph shows the output of the comparator. In the given example, the time of the comparator's high output is 4 × T s , which corresponds to the amount of the input charge, i.e., 4 × e. This charge-to-time concept has been used in the Wilkinson ADC (3) and also in the recent LSIs. (6) By removing the sample-and-hold and voltage-to-current converters from the system, the new circuit does not require an extra reset circuit and has no dead time since the stored charge in C det is automatically discharged during conversion. In addition, each conversion requires only a unit charge e and not the accumulated charge as a whole. Therefore, conversion can initiate before the complete charge transfer from the detector is concluded. Conversion is carried out in parallel with the charge drift and finishes simultaneously with the drift time of the charge by using a faster T s .

Materials and Methods
It is difficult to build such an ideal read-out circuit with real electronic components. Figure  2 shows a realistic circuit diagram of the ideal circuit that is implemented as a direct chargeto-digital converter (QDC). The CSA block is added to the ideal circuit, and this circuit injects charge to the feedback capacitor C fb instead of to the detector capacitance C det . The CIC is implemented by a switched capacitor network, CIC's unit charge is scaled up by the factor N for proportionate scaling in both the simulation and the experiment, and the clock frequency used in both the comparator and CIC represents the unit time T s . This architecture is similar to a first-order delta-sigma modulator. However, this QDC is designed in the time domain, while the delta-sigma modulator is designed in the frequency domain. Thereby, the main difference between the two is the unit charge of the CIC. The QDC uses a small charge corresponding to the least significant bit (LSB) as a single charge injection for charge read-out. On the other hand, the delta-sigma uses a large charge corresponding to the most significant bit (MSB) because it expects a frequency signal as the input; therefore, the format of the output digital code is also different compared with that of a QDC. The decoder of the delta-sigma is a decimator circuit, whereas the decoder of the QDC is a conditional counter.
The simulation is executed by a circuit simulator, LTspice. (7) The detector is replaced by a pulsed current source instead of a charge generated in the detector. An op-amp, a comparator, switches, and capacitors are implemented using ideal standard components in the LTspice library. An extra current source is added to the read-out node to represent the dark current of the detector, and the clock frequency for the simulation is set to 10 MHz.
The experimental circuit is built using discrete components. For the real physical circuit, a combination of 1 nF and 200 mV is used; therefore, the scaling factor N is equal to 4.0 × 10 6 , and V th is set to 200 mV according to the matching N. The clock frequency is set to 10 kHz to control nanofarad-order capacitance. The relationship between capacitance and voltage to generate charge is 10 fF and 5 mV, respectively, which corresponds to a photon energy of 1 keV with a germanium detector. The circuit is designed for a larger charge because the discrete component is much larger than the required charge scale.  The output of the CSA shows that fractions of the charge remain in C fb at the end of conversions because a voltage of the fraction of charge that is less than N × e does not exceed V th . This is a quantization error of this system and causes an offset in the subsequent conversion. In the special case when the scale factor N = 1, the quantization error disappears because there is no remaining fraction of charge in C fb . Figure 3(c) shows the effect of the dark current. The dark current has the same polarity as the input charge because they are in the same electric field. Consequently, the comparator reacts to the dark current and has a high output when the charge is accumulated up to the threshold charge by this current. On the other hand, the accumulated dark current in C fb is discharged by the CIC. The comparator outputs periodic highs as a result. Although the charge in C fb is affected by the dark current, it is similar to the effect of the quantization error for conversions. Therefore, the effects can be removed by cutting off the LSB from the output of the decoder. This simulated circuit shown in Fig. 2 works even for an actual X-ray/gamma ray detector that generates the dark current. Figure 4 shows the experimental results from the circuit described in Sect. 3. The probe channel 1 (blue) shows the output of the CSA that stores a test charge prior to clock initiation, channel 2 (cyan) shows the output of the comparator, and channel 3 (magenta) shows the clock applied to the CIC, which is initiated at 0 s on the oscilloscope. This result confirms the expected functionality of the proposed architecture to build a CIC with real electronic components, namely, a main block for charge read-out different from the delta-sigma modulator. The output of the CSA is stepped down by 200 mV, which is set by the combination of the specific capacitance and voltage described in Sect. 3. The charge injection is triggered by the output of the comparator because the comparator and the charge injection only work after initiation by the clock even if the charge stored in the CSA is more than the threshold charge. Moreover, the charge injection is synchronized with the clock, and this enables T s to control the rate of the charge injection. Therefore, the circuit shown in Fig. 2 is appropriate to build a real physical circuit for a direct QDC for X-ray/gamma ray photon counting. Although the 1 nF capacitor used in the experimental circuit is relatively large for sensing the charge corresponding to the energy of X-ray/gamma ray photons, a 10-fF-order capacitor is required and it can be fabricated by current CMOS technology. (4)

Conclusions
We introduced an ideal charge read-out circuit for X-ray/gamma ray photon counting based on charge injection and proposed a realistic implementation. This circuit reduces the loss due to conversion time by eliminating intermediate conversions because it is a direct conversion circuit unlike conventional circuits. The conversion behavior has been verified by simulating a direct QDC circuit. Moreover, the effect of the detector's dark current has been taken into consideration and a method for its compensation has been proposed. An experimental circuit has been built and tested with discrete components, and the possibility of a CIC block with real electronic components has been confirmed. Although the experimental circuit has been designed for a charge larger than the output charge of an actual X-ray/gamma ray detector, a QDC based on a CIC will work with an actual detector if the circuit is built with a small capacitor (10 fF) and smaller transistors constructed using CMOS technology.
From the proposed direct conversion, the circuit is simpler than an indirect conversion circuit and can be made smaller in size, which leads to lower power consumption. This circuit is suited for use in designing high-density imaging sensors. In addition, this architecture is valuable for the analysis of charge drift inside a detector because it ideally counts generated charges individually.