Comparison of Parasitic Capacitances of Packaged Cascode Gallium Nitride Field-effect Transistors

In this work, we examined the electrical characteristics of laboratory-fabricated cascode gallium nitride field-effect transistors (GaN FETs) and analyzed their parasitic capacitances. The calculated results were in good agreement with the experimental results and showed that commercial GaN FETs have superior switching performance, whereas laboratory-fabricated GaN FETs require further improvement.


Introduction
Wide-bandgap devices consisting of gallium nitride (GaN) or silicon carbide (SiC) have superior material properties that make them the most suitable candidate to replace Si-based transistors. (1)Since using these new power devices in GaN-based switching converter applications may be challenging, knowing the device characteristics is necessary.However, using GaN in power design fields with a high-switching condition engenders certain design challenges. (2)To assist designers in the switching application of GaN FETs, parasitic effect issues must be addressed.In recent years, several GaN FET device models have been reported in the field of power conversion.These models were partially collated and analyzed in the literature. (3)Among these models, the behavioral model can be developed through applying experimentally extracted parameters.To accurately evaluate switching performance, many previous studies have developed behavioral models to obtain realistic characteristic curves.Such models include a power loss estimation model; (4) a simple GaN power transistor model with temperature-and frequency-dependent inductor circuits, (5) which exhibited strong static characteristics; and a model considering detailed parasitic inductance and cascode capacitance. (6,7)ther models include one with turn-off resistance that was developed for sorting device uniformity. (8)The goal of all the aforementioned studies was to develop GaN FET models that are more practical than real power devices.The goal was the same for the present study.In previous studies, several laboratory-fabricated GaN FETs such as those based on flip-chip packaging and wire bonding have been proposed. (9,10)The electrical characteristics of D-mode and cascode devices have also been studied. (10)However, parasitic effects on laboratoryfabricated cascode GaN FETs have not been determined in any of the aforementioned studies.GaN-based sensors have been proposed for gas sensing, pH measurement, heavy metal detection, biotoxin sensing, and biomedical applications, owing to their promising results including fast response, small device size, and chemical and thermal stability. (11,12)Sensors with rapid response need fast switching performance.The parasitic capacitance of a GaN FET is a significant factor in determining the switching response during the switching transition.The faster the gate charge is supplied, the faster the device will change the switching transition. (13)he present study involved two stages.First, the device structure of metal-insulatorsemiconductor high-electron-mobility transistors (MIS-HEMTs) was introduced, and static characterization was performed using a curve tracer and a capacitance-voltage (C-V) analyzer. (14)econd, the analysis of parasitic capacitances on the fabricated cascode GaN FET model was demonstrated.

Device structure of MIS-HEMT
Figure 1(a) shows a simplified schematic of the fabricated AlGaN/GaN MIS-HEMT used in this study.The thicknesses of the Al 0.23 Ga 0.77 N and GaN layers are 20 nm and 2.1 μm, respectively.The gate-to-drain spacing is 17 μm and the gate-to-source spacing is 3 μm.The gate length is 1 μm and the gate width is 1 mm.The device has 80 fingers, so the total gate width is 80 mm.The detailed device fabrication information is shown in Ref. 10.The MIS-HEMT is a normally-on device; without an applied negative gate-source voltage, the device is in the on-state.Connection to a low-voltage cascode metal-oxide-semiconductor fieldeffect transistor (LV MOSFET) allows normally-on MIS-HEMT devices to act as normallyoff devices, as shown in Fig. 1(b).The MIS-HEMT was a 600 V, 330 mΩ device, (10) and the LV MOSFET chosen was a 30 V OptiMOS TM3 with an R DS(on) of 3.1 mΩ. (15)Studies have demonstrated the characteristics of laboratory-fabricated D-mode and cascode GaN FETs.Owing to variations in device fabrication, wire bonding, and packaging, device characteristics must be measured to obtain detailed device information.For comparison, commercial cascode GaN FETs are used in this study. ( 16

Electrical characteristics of cascode GaN FETs
The static characteristics, namely the transfer characteristics (I DS -V GS ), and parasitic capacitances of cascode GaN FETs, are described in the following section.From the static characteristics, the plateau voltage (V PL ) in the gate charge curve can be read from the transfer characteristic graph with the test current whereas the gate charge can be derived from parasitic capacitance curves.Gate charge information can predict the switching behavior.

Transfer characteristics (I DS -V GS )
The transfer characteristics of the commercial GaN FET and fabricated D-mode MIS-HEMT for various V GS values are tested in the range of −25 to 1 V measured at 1 V increments with a V DS of 10 V, similarly to the commercial and fabricated cascode GaN FET transfer characteristics for V GS values ranging from 0 to 6 V measured at 1 V increments with a V DS of 10 V.

Parasitic capacitances (C gs , C gd , and C ds )
The parasitic capacitances C iss , C oss , and C rss can be represented as C iss = C gs + C gd , C oss = C gs + C ds , and C rss = C gd , respectively.The detailed measurements of the parasitic capacitances are explained in Ref. 8. The measurements were conducted within an AC frequency range of 100 kHz-1 MHz.C gs was measured at 100 kHz, whereas C ds and C gd were measured at 1 MHz with an oscillation level of 30 mV.

Analysis of cascode parasitic capacitances
Figure 2 shows the equivalent capacitance of the cascode GaN FET structure in this study.Capacitances labeled with the subscripts "C", "M", "J", and "D" represent cascode GaN FET, LV MOSFET, MIS-HEMT, and SiC Schottky barrier diode (SBD), respectively.The cascode parasitic capacitances are divided into three regions: As the MOSFET drain-source voltage is smaller than the absolute value of the first MIS-HEMT pinch-off-voltage (V P_J1 ) (V DS_M < |V P_J1 |), the MIS-HEMT channel is conducting because of its normally-on characteristics.The cascode input capacitance (C iss_C ) is the sum of C gs_M and C gd_M in the LV MOSFET represented as Eq. ( 1).The transfer capacitance (C rss_C ) is the C gd_M of the LV MOSFET represented as Eq. ( 2).The conducting channel of the MIS-HEMT connects the output capacitance of the MOSFET (C oss_M ) [gate-drain capacitance (C gd_M ) and drain-source capacitance (C ds_M )] in parallel with the input capacitance of the MIS-HEMT (C iss_J ) [gate-drain capacitance (C gd_J ) and gate-source capacitance (C gs_J )], and the output capacitance of the cascode can be represent as Eq.(3): As the drain-to-source voltage of the MOSFET (V ds_M ) reaches above the first pinch-off voltage of the MIS-HEMT (V P_J1 ) and below the second pinch-off voltage of the MIS-HEMT , the first MIS-HEMT starts to block voltage.In the second stage, the cascode input capacitance (C iss_C,2 ) is the sum of C gs_M and C gd_M in the series of C ds_ M , C ds_J , and C gs_J1 , which are in parallel with each other, represented as Eq. ( 4), the transfer capacitance (C rss_C,2 ) is C gd_M in the series of C ds_J , represented as Eq. ( 5), and the cascode output parasitic capacitance (C oss_C,2 ) is the sum of C gd_J1 , C gs_J1 , C gd_J2 , C D , and C ds_J in the series of C gd_M , C ds_M , and C gs_J1 , which are in parallel with each other, represented as Eq. ( 6): As the drain-to-source voltage of the MOSFET (V ds_M ) is above the second pinch-off voltage of the MIS-HEMT (V P_J2 ) (V DS_M ≥ |V P_J2 |), the second MIS-HEMT starts to block voltage.In the third stage, the cascode input capacitance (C iss_C,3 ) and transfer capacitance (C rss_C,3 ) are the same as the cascode input capacitance (C iss_C,2 ) and transfer capacitance (C rss_C,2 ) in the second stage represented as Eq. ( 4) and Eq. ( 5), whereas the cascode output parasitic capacitance (C oss_C,3 ) is the sum of C gd_J2 , C D , and C ds_J in the series of C gd_M , C ds_M , and C gs_J1 , which are in parallel with each other, represented as Eq. ( 7):

Gate charge curve (V GS -Q GS )
The test fixture employed for measuring the gate charge curve, which can be taken from the oscilloscope, is illustrated in Ref. 17.A plot of gate-to-source voltage versus time measured on the oscilloscope can be converted to a plot of gate-to-source voltage versus gate charge because of the relationship Q G = I G × t.In the test, the drain-source voltage V DD was set to 100 V and the load resistance R L to 10 Ω.The load current I D was set to 10 A because the turn-on resistance R DS(on) of the test device was low.The constant gate current I g was set to approximately 1 mA by using a supply voltage of V CC = 10 V, a pnp bipolar junction transistor (BJT), a 3.3 V Zener diode (V ZD ), and two resistors, 2.7 kΩ (R E ) and 10 kΩ (R S ).

Results
The red triangles and blue circles in the figure represent the plots for I DS versus V GS for the fabricated D-mode and cascode devices, respectively, as shown in Fig. 3.The threshold voltage was determined according to the intersection between the tangent and horizontal axis.The threshold voltage of the fabricated D-mode MIS-HEMT was −20 V, whereas that of the cascode device was 1.9 V.The threshold voltage of the commercial GaN FET was about 3 V.
Figure 4 illustrates the parasitic capacitances of the fabricated D-mode MIS-HEMT and cascode GaN FETs.In the D-mode MIS-HEMT, the input capacitance C iss , output capacitance C oss , and reverse transfer capacitance C rss at V GS = −25 V (V G = 0, V S = 25 V) and V D = 125 V (relative drain-to-source voltage V DS = 100 V) were 56, 50.6, and 8.64 pF, respectively.The corresponding values in the cascode GaN FET at V GS = 0 V and V DS = 0 V were 4350, 5250, and 505 pF; and those at V GS = 0 V and V DS = 100 V were 4350, 110, and 1.84 pF.The parasitic capacitances of the cascode GaN FET were higher than those of the D-mode MIS-HEMT because of the parasitic capacitance of the cascode LV MOSFET.The input capacitance (C iss ) and output capacitance (C oss ) of the fabricated GaN FET were approximately one order higher than those of the commercial GaN FET, whereas the transfer capacitance (C rss ) values of the two devices were the same when the V DS biasing voltage was above 20 V. V J and M were extracted through curve fitting with numerical analysis software (MATLAB) from the measured C-V characteristics of the device.The commercial cascode capacitance considerably decreased at 22 V [Fig.4(a)], whereas the fabricated cascode capacitance decreased abruptly at 20 V [Fig.4(b)], which is exactly the threshold voltage V TH_GaN of the GaN FETs.The V TH values of the first and second junction field-effect transistors (JFETs) for commercial GaN FETs were chosen as 21 and 22 V, whereas those for the fabricated GaN FETs were chosen as 19 and 20 V, respectively.After the parasitic capacitances have been created, the simulation can be applied to obtain the created parasitic capacitances of the transistors by following the steps in Ref. 18.The measurement and simulation exhibited excellent agreement.
Because the constant current of 1 mA is charged into the gate, each division of the horizontal axis can be read in nanocoulombs when the time scale is expressed in microseconds.The Q GD charge of the fabricated cascode GaN FET (3.66 nC) is higher than those of the commercial cascode GaN FET (2.07 nC), but lower than those of CoolMOS (16.39 nC).A lower Q GS means that the switching drainto-source current waveform has a shorter current transition period, and a lower Miller charge shows that the switching drain-to-source voltage waveform has a shorter voltage transition period.The lower the charge required, the shorter the transition will take, and the lower the switching losses. (13,20)

Conclusions
In this study, we examined GaN FET electrical characteristics using C-V plot, gate charge curve, and their switching performance.We also analyzed the cascode GaN FET capacitance.GaN FETs with lower parasitic capacitance have lower gate charge requirements, enabling faster switching.The laboratory-fabricated cascode GaN FET has the largest input parasitic capacitance (C iss ); thus, we should choose an optimal LV MOSFET to improve the switching performance.

Figure 6 (Fig. 4 .
Figure4illustrates the parasitic capacitances of the fabricated D-mode MIS-HEMT and cascode GaN FETs.In the D-mode MIS-HEMT, the input capacitance C iss , output capacitance C oss , and reverse transfer capacitance C rss at V GS = −25 V (V G = 0, V S = 25 V) and V D = 125 V (relative drain-to-source voltage V DS = 100 V) were 56, 50.6, and 8.64 pF, respectively.The corresponding values in the cascode GaN FET at V GS = 0 V and V DS = 0 V were 4350, 5250, and 505 pF; and those at V GS = 0 V and V DS = 100 V were 4350, 110, and 1.84 pF.The parasitic capacitances of the cascode GaN FET were higher than those of the D-mode MIS-HEMT because of the parasitic capacitance of the cascode LV MOSFET.The input capacitance (C iss ) and output capacitance (C oss ) of the fabricated GaN FET were approximately one order higher than those of the commercial GaN FET, whereas the transfer capacitance (C rss ) values of the two devices were the same when the V DS biasing voltage was above 20 V. V J and M were extracted through curve fitting with numerical analysis software (MATLAB) from the measured C-V characteristics of the device.The commercial cascode capacitance considerably decreased at 22 V [Fig.4(a)],whereas the fabricated cascode capacitance decreased abruptly at 20 V [Fig.4(b)], which is exactly the threshold voltage V TH_GaN of the GaN FETs.The V TH values of the first and second junction field-effect transistors (JFETs) for commercial GaN FETs were chosen as 21 and 22 V, whereas those for the fabricated GaN FETs were chosen as 19 and 20 V, respectively.After the parasitic capacitances have been created, the simulation can be applied to obtain the created parasitic capacitances of the transistors by following the steps in Ref.18.The measurement and simulation exhibited excellent agreement.Because the constant current of 1 mA is charged into the gate, each division of the horizontal axis can be read in nanocoulombs when the time scale is expressed in microseconds.Figure5illustrates the gate charge waveforms of the commercial and fabricated cascode GaN FETs.Figure6(a) shows the measured parasitic capacitance.The laboratory-fabricated cascode GaN FET (TO-257) has the largest input parasitic capacitance (C iss ) compared with the commercial cascode GaN FET and CoolMOS.The laboratory-fabricated cascode GaN FET with different voltage (~−10 V) and power quad flat no lead (PQFN) package also faces the large input parasitic capacitance problem because it has the same cascode LV MOSFET.The input parasitic capacitance of the cascode LV MOSFET dominates; therefore, the optimal LV MOSFET should be chosen.Nevertheless, it is still better than the CoolMOS when considering the Q GD charge.Figure 6(b) shows the Miller charge (Q GD ) values of the fabricated cascode GaN FET, commercial cascode GaN FET, and CoolMOS.