S&M Young Researcher Paper Award 2020
Recipients: Ding Jiao, Zao Ni, Jiachou Wang, and Xinxin Li [Winner's comments]
Paper: High Fill Factor Array of Piezoelectric Micromachined
Ultrasonic Transducers with Large Quality Factor

S&M Young Researcher Paper Award 2021
Award Criteria
Notice of retraction
Vol. 32, No. 8(2), S&M2292

Print: ISSN 0914-4935
Online: ISSN 2435-0869
Sensors and Materials
is an international peer-reviewed open access journal to provide a forum for researchers working in multidisciplinary fields of sensing technology.
Sensors and Materials
is covered by Science Citation Index Expanded (Clarivate Analytics), Scopus (Elsevier), and other databases.

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Chopper-stabilized Multipath Instrumentation Amplifier with Output Voltage Offset Compensation Using R-2R DAC

Hyunwoo Heo, Hyungseup Kim, Donggeun You, Yongsu Kwon, Dong-il “Dan” Cho, and Hyoungho Ko

(Received April 17, 2020; Accepted April 8, 2021)

Keywords: chopper-stabilized, multipath amplifier, high-frequency path, low-frequency path, R-2R DAC, ripple reduction loop (RRL)

This paper presents a 3-opamp resistive bridge sensor analog front-end (AFE) integrated circuit (IC) with offset voltage compensation using an R-2R digital-to-analog converter (DAC). The proposed IC is implemented with a 3-opamp instrumentation amplifier (IA) to achieve high gain, high input impedance, and linearity. The two amplifiers in the first stage are multipath amplifiers with a chopper stabilization technique and ripple reduction loop (RRL). The chopper stabilization technique reduces 1/f flicker noise and DC offset, and the RRL mitigates the output ripple voltage resulting from the chopper stabilization technique. The multipath amplifier scheme compensates the notch characteristic in the frequency response caused by the RRL. A fully differential amplifier with a class-AB output stage is used in the second stage to achieve power efficiency. The 12-bit R-2R DAC is implemented to compensate the offset of the second-stage output of the IA. The IA gain can be controlled from 12 to 48 dB using the 2-bit and 3-bit programmable feedback resistor arrays in the first and second stages, respectively. The proposed IC is designed with a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and has an active area of 7.2 mm2. The simulated input-referred noise is 36.7 nV/√Hz at a frequency of 1 Hz and the simulated input offset voltage is 2.2 μV.

Corresponding author: Hyoungho Ko




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