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Vol. 32, No. 8(2), S&M2292

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Sensors and Materials, Volume 32, Number 5(3) (2020)
Copyright(C) MYU K.K.
pp. 1889-1897
S&M2225 Research Paper of Special Issue
Published: May 31, 2020

Characteristics of Tunnel Field-effect Transistors under Power-on Electrostatic Discharge and Electrical Overstress Conditions [PDF]

Zhaonian Yang, Pan Mao, Yue Zhang, Ningmei Yu, and Juin J. Liou

(Received July 31, 2019; Accepted February 6, 2020)

Keywords: electrical overstress (EOS), electrostatic discharge (ESD), tunnel field-effect transistor (TFET), power-on conditions, temperature

The power-on electrostatic discharge (ESD) and electrical overstress (EOS) events are causing an increasing number of failures in modern integrated circuits (ICs). Tunnel field-effect transistors (TFETs) are considered as a better choice than shallow trench isolation diodes in whole-chip ESD protection networks. We have investigated the characteristics of TFETs under power-on ESD and EOS conditions by numerical simulation. The impact of an elevated ambient temperature, variations in current rise time and discharge duration, and the device structure on the triggering voltage and failure current are evaluated. The obtained results are discussed with detailed physical insights.

Corresponding author: Zhaonian Yang

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Cite this article
Zhaonian Yang, Pan Mao, Yue Zhang, Ningmei Yu, and Juin J. Liou, Characteristics of Tunnel Field-effect Transistors under Power-on Electrostatic Discharge and Electrical Overstress Conditions, Sens. Mater., Vol. 32, No. 5, 2020, p. 1889-1897.

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